Rosetta IP provides a comprehensive solution for SoC development by:
• Turning innovative VLSI designs into IP Cores, based on
objective quality assessment
• Ensuring fast, smooth & predictable integration of the
Cores into its targeted system
White Paper: Application Specific IP - Ensuring Semiconductor IP Quality
One of the major barriers for Semiconductor IP commercialization is to provide evidence for an IP's quality. A common approach by IP vendors is to prove the quality of their IP in a test chip. Usually the Die contains the IP block separated from the System-on-a-Chip (SoC).
June 2011:
• Rosetta IP to Present Energy Efficient Ethernet Physical Layer
IP core at DAC
May 2011:
• POF-Plus final report was submittedto the FP7 project officer
• Rosetta IP certified by Applied Materials as an approve vendor
April 2011:
• Rosetta IP and Vitesse Semiconductors signed
partnership agreement
• Rosetta IP signed IP agreement with a leading
European semiconductor vendor
• Rosetta IP joined the IP SOC advisory board
Events 2011:
• IP-SOC : Grenoble
• DAC : San Diego
• Chipex : Tel Aviv
• OFC : Los Angeles
